Communication channels are seldom ideal. Intersymbol interference may result due to channels having a bandwidth smaller than the signal bandwidth, as well as signal reflections from discontinuities on the communication channel. Channel equalization is a method to help mitigate this type of interference. In particular, a decision feedback equalizer (DFE) utilizes past decisions of the receiver to help mitigate intersymbol interference arising from signal reflections. Decision feedback equalizers find application in many communication systems, such as for example a computer server or system such as that depicted in FIG. 1. FIG. 1 provides a high-level abstraction of a portion of a computer server or system, where microprocessor 102 resides on board 104 and communicates with memory 106 on board 108. The communication is by way of striplines on backplane 110. Backplane 110 is connected to boards 104 and 108 by connectors 112. Not shown in FIG. 1 are other memory units and microprocessors, where the various microprocessors and memory units may communicate to one another so as to access or write data and instructions.
Communication of signals over backplane 110 may be modeled by transmission line theory. Often, the signaling is based upon differential signaling, whereby a single bit of information is represented by a differential voltage. For example, FIG. 2a shows drivers 202 and 204 driving transmission lines 206 and 208, respectively. For differential signaling, drivers 202 and 204 drive their respective transmission lines to complementary voltages. Typical curves for the node voltages at nodes n1 and n2 for a bit transition are provided in FIG. 2b, where the bit transition is indicated by a dashed vertical line crossing the time axis. The information content is provided by the difference in the two node voltages.
For short-haul communication, such as for the computer server in FIG. 1, the signal-to-noise ratio is relatively large. If the transmission lines are linear, time-invariant systems having a bandwidth significantly greater than that of the transmitted signal, and if there are no impedance mismatches, then a relatively simple receiver architecture may be employed to recover the transmitted data. Such a receiver is abstracted by comparator 210, which provides a logic signal in response to the difference in the two received voltages at ports 212 and 214.
However, every transmission line has a finite bandwidth, and for signal bandwidths that are comparable to or exceed the transmission line (channel) bandwidth, intersymbol interference may present a problem. Furthermore, actual transmission lines may have dispersion, whereby different spectral portions of a signal travel at different speeds. This may result in pulse spreading, again leading to intersymbol interference. As a practical example, for high data rates such as 10 Gbs (Giga bits per second), the transmission lines used with backplanes or motherboards are such that intersymbol interference is present. Furthermore, there may be transmission lines mismatches, causing signal reflections, which may contribute significantly to intersymbol interference.
A decision feedback equalizer may be used in conjunction with other filters, such as an FIR (Finite Impulse Response) receiver, to help mitigate intersymbol interference. It is desirable for a DFE to allow for bi-directional signaling for simultaneous transmission and reception, to be easily integrated with a FIR equalizer, and to allow for high data rate signaling.